(a) Field of the Invention
The present invention relates to a semiconductor device including a fin-channel recess-gate MISFET (metal-insulator-semiconductor field-effect-transistor) and a method for manufacturing the semiconductor device including the fin-channel recess-gate MISFET.
(b) Description of the Related Art
Recently, new models of MISFET including a fin-channel MISFET having a fin channel and a recess-gate MISFET having a recess gate are expected to achieve a finer pattern size in a semiconductor device. The techniques for the fin-channel MISFET and recess-gate MISFET may be applied to a single MISFET to achieve a fin-channel recess-gate MISFET. FIGS. 7A to 11A show consecutive steps of a conceivable (or comparative) process for manufacturing a semiconductor device including such a fin-channel recess-gate MISFET. FIGS. 7B to 11B are sectional views taken along line B-B in FIGS. 7A to 11A, respectively, and FIG. 10C is a sectional view taken along line C-C in FIG. 10A.
The structure shown in FIGS. 7A and 7B is formed by the following steps. An array of dielectric film patterns 12, one of which is shown in those drawings, are formed on a silicon substrate 11 by a photolithographic and dry etching technique using a photoresist mask pattern. Subsequently, a trench 18 is formed on the surface region of the silicon substrate 11 by a dry etching technique using the dielectric film patterns 12 as an etching mask, followed by depositing an isolation film 13 within the trench 18 to form a shallow trench isolation (STI) structure. The height (h13) of the dielectric film 12 as measured from the bottom of the trench 18 of the STI structure to the top of the dielectric film 12 is set at a specific value in consideration of the dimensions of the fin channel and recess gate.
For example, the height h13 of the isolation film 13 is set at 400 nm assuming that the thickness of dielectric film patterns 12 is 100 nm, the height of fin channel is 100 nm, the depth of gate trench is 100 nm, and the depth of shallow trench 18 needed for isolation between adjacent device regions is 100 nm in the final structure of MISFETs. The isolation film 13 and shallow trench 18 are then polished using a CMP (chemical-mechanical-polishing) technique using the dielectric film patterns 12 as a stopper, thereby forming the structure shown in FIGS. 7A and 7B.
Subsequently, a photoresist pattern 21 having an opening in the central area of the dielectric film patterns 12 is formed by a photolithographic technique. The width d2 of the opening in the dielectric film patterns 12 is set at 50 nm. The dielectric film patterns 12 are then etched using the photoresist pattern 21 as an etching mask, to form an opening 19 in the dielectric film patterns 12 for exposing therethrough the silicon substrate 11. The resultant structure is shown FIGS. 8A and 8B.
Subsequently, the photoresist pattern 21 is removed, and a dry etching process is performed to the silicon substrate 11 by using the dielectric film patterns 12 as an etching mask, to thereby form a recess 23 for the gate electrode within the silicon substrate 11. The depth h2′ of the recess 23 is set at 100 nm, for example. A wet etching process is then conducted to the dielectric film patterns 12 and the isolation film 13 of the STI structure. At this stage, the amount of wet etching is controlled so that the dielectric film patterns 12 are entirely removed and the height h 13′ of the isolation film 13 remaining after the wet etching is 100 nm, for example. The resultant structure is shown in FIGS. 9A and 9B.
Thereafter, a gate insulation film 14 is formed on the exposed surface of the silicon substrate 11 by using a thermal oxidation technique, for example, followed by deposition of a gate electrode material. The thickness of the deposited gate electrode material is larger than the width d2 of the recess 23 in the silicon substrates 11, whereby the entire depth of the recess 23 is filled with the gate electrode material. Thereafter, the gate electrode material is polished using a CMP technique for planarization of the top surface thereof. The top surface of the gate electrode material has a height of h5 with respect to the top surface of the silicon substrate 11. The gate electrode material is then patterned to form a gate electrode (gate electrode line) 15 having a depth d5 of 70 nm, for example, which is larger than the width d2 of the recess 23, whereby both the edges of the gate electrode (i.e., gate electrode line) 15 are outside the recess 23. This structure is shown in FIGS. 10A and 10B, and also shown in FIG. 10C which is taken along line C-C in FIG. 10A, i.e., along the extending direction of the gate electrode line 15. The gate electrode 15 encircles the fin channel 20 at the top and side surfaces of the fin channel 20, as shown in FIG. 10C.
An insulation film is then formed on the entire surface including the surface of the gate electrode 15, followed by etch-back thereof to form a sidewall insulation film 16 on the sidewall of the gate electrode 15. An interlevel dielectric film and contact plugs penetrating therethrough are then formed to complete the structure of MISFETs, as shown in FIGS. 11A and 11B.
The fin-channel MISFET is described in Patent Publications Nos. JP-2004-533728A, -2005-236305A and -2006-13521A, for example. The recess-gate MISFET is described in a literature “Symposium on VLSI Technology Digest of Technical Papers”, P 11-12, 2003 presented by J. Y. Kim et al.
In the comparative process for manufacturing the fin-channel recess-gate MISFET as described above, there is a problem in that the trench 18 of the STI structure during embedding the isolation film 13 within the trench 18 has a large aspect ratio to thereby incur occurrence of a void within the isolation film 13. The void, if formed in the isolation film 13, degrades the characteristics of the isolation film 13 and may increase the leakage current of the MISFET.